Ultra-Low-Power Digital Circuit Design

Subthreshold source-coupled logic (STSCL) is a logic family that contains a constant bias current in each logic gate. Logic operation is based on the steering of this current towards one of two load resistors using subthreshold dierential pairs. STSCL was proposed for its low power consumption due to the small voltage signal swing, as well its suitability for congurable circuits. In this work, the feasibility of an ECC processor using subthreshold source-coupled logic was studied. It was shown that the STSCL design ow can be successfully applied to a real-world design. However, comparison with a standard low-voltage CMOS implementation showed that STSCL in its current state is not as energy-ecient as CMOS. Two main reasons for this have been identied: The most consequential problem in the design of STSCL circuits in deep sub-micron technologies are device mismatches. They make it necessary to use transistors much larger than the minimum size, leading to increased device capacitances as well as interconnect parasitics due to the larger overall area of the circuits. The special load devices used for STSCL further aggravate the problem of large cell areas, since they require two isolated n-wells in the layout of each logic gate. The other issue that has been identied is the importance of the logic depth of the design. Since the power dissipation in STSCL is directly proportional to the speed of the individual gates, a high logic depth requires each gate to be faster, which leads to poor performance in comparison to CMOS. Even in its current implementation, STSCL oers some of the expected advantages over CMOS. Most notably, the replica bias circuit used to generate the bias voltages for the current source and load resistors of each gate makes it possible to use the same circuit over a wide range of target frequencies, independent of the supply voltage. As expected, the current prole of STSCL gates is very at; this is an important advantage for cryptographic applications where an attacker might try to gain information on the data being processed by studying the supply current. The performance issues with the present design suggest that certain steps be taken to improve the library and design ow: Redesigning a STSCL standard cell library with less conservative device sizing would somewhat reduce the cell area and could help amend the problems of large interconnect capacitance. Further improvements could be made by building a more complete standard …